(1) Field of the Invention
The present invention relates to the fabrication methods used for semiconductor devices, and more specifically to an improved process allowing for contact between the active silicon device region and the overlying metal lines.
(2) Description of Prior Art
A major objective of the semiconductor industry is to achieve higher performing devices while still decreasing the cost of the semiconductor chip. The ability to place more chips on a wafer has significantly reduced the cost of semiconductor chips. This has been made possible by the industry being able to still increase device density, while maintaining, or increasing, the total number of devices on the smaller silicon chips. Micro-miniaturation, of specific device elements, has been a major factor in the trend to smaller chip sizes. The ability of the semiconductor community to decrease critical device dimensions has allowed the attainment of not only smaller chips, but also resulted in higher performing devices. The latter is accomplished by reducing the performance erroding resistances and capacitances, resulting with larger device areas.
The obvious factor in the reduction of critical device dimension, leading to improved device density, has been the advances in the photo lithographic discipline. More sophisticated exposure cameras, as well as more sensitive photoresist materials, have allowed sub-micron images in photoresist to be routinely achieved. In addition, similar advances in plasma etching disciplines have allowed the successful transfer of the sub-micron images, in photoresist, to an underlying material used for the construction of specific semiconductor chips, to occur. Other semiconductor disciplines, such as ion implantation, (I/I), as well as low pressure chemical vapor deposition, (LPCVD), have also been major, factors in meeting the micro-miniaturization objective. Thus advances in specific semiconductor process sectors have resulted in the increasing number of devices per chip, while still either maintaining, or reducing chip size.
In addition to reducing chip size via advances in semiconductor disciplines, further reductions have been experienced via development of specific processes, such as sidewall spacers and buried contact schemes. These processes have resulted in the reduction of device area, without the use of photoresist or plasma etching breakthroughs. Another process sequence used to conserve precious silicon area is the polysilicon contact plug concept. Communication between an underlying active device region, and an overlying interconnect metallury, is a critical part of the semiconductor fabrication process. Several vital aspects have to be satisfied to ensure device; density, performance and reliability. For example if to much area is consumed in achieving the connection, between the silicon and metal areas, device density will be decreased. Also if the spacing between contacts becomes to large, performance will suffer. Finally if compromises are made in the material chosen for the contact, reliability issues can arise. Therefore efforts have been directed to the use of polysilicon contacts, for this critical fabrication step. Bersom, etal, in U.S. Pat. No. 5,196,373, and Nakamo, etal., in U.S. Pat. No. 5,183,781, describe a polysilicon contact process, however without showing the exact details needed to successfully fabricate this structure. Also, Boyd, etal., in U.S. Pat. No. 5,316,978 show a polysilicon contact process using a complex and costly chemical mechanical polishing, (CMP), technique for polysilicon removal. The process described in this invention will detail a novel, non-costly technique, employed to create polysilicon contacts to active silicon device regions.